variables

This table contains all the variables of all the datasets we have at Our World In Data. Note that this includes only the information about the variables like name and default display settings, not the data itself.

Data license: CC-BY

3 rows where sourceId = 29581 sorted by id descending

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id ▲ name unit description createdAt updatedAt code coverage timespan datasetId sourceId shortUnit display columnOrder originalMetadata grapherConfigAdmin shortName catalogPath dimensions schemaVersion processingLevel processingLog titlePublic titleVariant attributionShort attribution descriptionShort descriptionFromProducer descriptionKey descriptionProcessing licenses license grapherConfigETL type sort dataChecksum metadataChecksum
737090 Design % The Design phase encompasses the specification, logic design, physical design, along with validation and verification. The specification outlines the intended operation of the chip within its target system. The logic design phase constructs a schematic model featuring interconnected electrical components. The physical design converts this schematic into a tangible layout of these components and their interconnecting wires. Finally, the design undergoes a validation and verification process to ensure its functionality. 2023-07-07 12:01:27 2024-07-08 17:49:16     2021-2021 The Semiconductor Supply Chain Assessing National Competitiveness (CSET, 2022) 6118 CSET (2022) 29581 % 
{
    "unit": "%",
    "shortUnit": "%"
}
 0     design grapher/artificial_intelligence/2023-07-07/semiconductors_cset/semiconductors_cset#design   1                 
[]
         int 
[]
 3158d1b5f84bf49037e76906fd4372ef 0323d52fd5e92608b0e8b76a9ac4f02c
737089 Fabrication % The Fabrication stage morphs these designs into tangible chips. Semiconductor manufacturing plants, known as 'fabs', process the wafers in two primary steps: forming transistors and other electrical devices within silicon wafer layers and creating metallic interconnections among the electrical devices in the insulating layers above the silicon. 2023-07-07 12:01:27 2024-07-08 17:49:16     2021-2021 The Semiconductor Supply Chain Assessing National Competitiveness (CSET, 2022) 6118 CSET (2022) 29581 % 
{
    "unit": "%",
    "shortUnit": "%"
}
 0     fabrication grapher/artificial_intelligence/2023-07-07/semiconductors_cset/semiconductors_cset#fabrication   1                 
[]
         int 
[]
 be306bcc260bce71d570f1d7a6ec4227 ad2e51f14bbe1ac2d2ac41f00787962c
737088 Assembly, testing and packaging % The completion of the fabrication process yields a finished wafer housing numerous chips in a grid pattern. The subsequent stage is Assembly, which involves testing and packaging. The wafer undergoes division into individual chips or 'dies.' Each chip is mounted on a frame, wired to facilitate connection with external devices, and housed within a protective case. This stage results in the familiar image of a rectangular, dark grey chip with metal pins around the periphery. The chip also undergoes testing to confirm its operational capacity. Historically, Assembly, Test, and Packaging (ATP) was considered a lower value stage. However, with the exponential rise in transistor densities within logic chips, packaging has progressively become a key determinant of chip performance. 2023-07-07 12:01:27 2024-07-08 17:49:16     2021-2021 The Semiconductor Supply Chain Assessing National Competitiveness (CSET, 2022) 6118 CSET (2022) 29581 % 
{
    "unit": "%",
    "shortUnit": "%"
}
 0     assembly__testing__and_packaging__atp grapher/artificial_intelligence/2023-07-07/semiconductors_cset/semiconductors_cset#assembly__testing__and_packaging__atp   1                 
[]
         int 
[]
 7ca65a5ea9f158d48885a18083ce88fc bb36b93d961be705d315ab4198d9066f

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CREATE TABLE "variables" (
	"id" INTEGER PRIMARY KEY AUTOINCREMENT,
	"name" VARCHAR(750) NULL  ,
	"unit" VARCHAR(255) NOT NULL  ,
	"description" TEXT NULL  ,
	"createdAt" DATETIME NOT NULL DEFAULT CURRENT_TIMESTAMP ,
	"updatedAt" DATETIME NULL  ,
	"code" VARCHAR(255) NULL  ,
	"coverage" VARCHAR(255) NOT NULL  ,
	"timespan" VARCHAR(255) NOT NULL  ,
	"datasetId" INTEGER NOT NULL  ,
	"sourceId" INTEGER NULL  ,
	"shortUnit" VARCHAR(255) NULL  ,
	"display" TEXT NOT NULL  ,
	"columnOrder" INTEGER NOT NULL DEFAULT '0' ,
	"originalMetadata" TEXT NULL  ,
	"grapherConfigAdmin" TEXT NULL  ,
	"shortName" VARCHAR(255) NULL  ,
	"catalogPath" VARCHAR(767) NULL  ,
	"dimensions" TEXT NULL  ,
	"schemaVersion" INTEGER NOT NULL DEFAULT '1' ,
	"processingLevel" VARCHAR(30) NULL  ,
	"processingLog" TEXT NULL  ,
	"titlePublic" VARCHAR(512) NULL  ,
	"titleVariant" VARCHAR(255) NULL  ,
	"attributionShort" VARCHAR(512) NULL  ,
	"attribution" TEXT NULL  ,
	"descriptionShort" TEXT NULL  ,
	"descriptionFromProducer" TEXT NULL  ,
	"descriptionKey" TEXT NULL  ,
	"descriptionProcessing" TEXT NULL  ,
	"licenses" TEXT NULL  ,
	"license" TEXT NULL  ,
	"grapherConfigETL" TEXT NULL  ,
	"type" TEXT NULL  ,
	"sort" TEXT NULL  ,
	"dataChecksum" VARCHAR(64) NULL  ,
	"metadataChecksum" VARCHAR(64) NULL,
	FOREIGN KEY("datasetId") REFERENCES "datasets" ("id") ON UPDATE RESTRICT ON DELETE RESTRICT,
	FOREIGN KEY("sourceId") REFERENCES "sources" ("id") ON UPDATE RESTRICT ON DELETE RESTRICT
);
CREATE UNIQUE INDEX "idx_catalogPath" ON "variables" ("catalogPath");
CREATE UNIQUE INDEX "unique_short_name_per_dataset" ON "variables" ("shortName", "datasetId");
CREATE UNIQUE INDEX "variables_code_fk_dst_id_7bde8c2a_uniq" ON "variables" ("code", "datasetId");
CREATE INDEX "variables_datasetId_50a98bfd_fk_datasets_id" ON "variables" ("datasetId");
CREATE UNIQUE INDEX "variables_name_fk_dst_id_f7453c33_uniq" ON "variables" ("name", "datasetId");
CREATE INDEX "variables_sourceId_31fce80a_fk_sources_id" ON "variables" ("sourceId");