variables: 737090
Data license: CC-BY
This data as json
id | name | unit | description | createdAt | updatedAt | code | coverage | timespan | datasetId | sourceId | shortUnit | display | columnOrder | originalMetadata | grapherConfigAdmin | shortName | catalogPath | dimensions | schemaVersion | processingLevel | processingLog | titlePublic | titleVariant | attributionShort | attribution | descriptionShort | descriptionFromProducer | descriptionKey | descriptionProcessing | licenses | license | grapherConfigETL | type | sort | dataChecksum | metadataChecksum |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
737090 | Design | % | The Design phase encompasses the specification, logic design, physical design, along with validation and verification. The specification outlines the intended operation of the chip within its target system. The logic design phase constructs a schematic model featuring interconnected electrical components. The physical design converts this schematic into a tangible layout of these components and their interconnecting wires. Finally, the design undergoes a validation and verification process to ensure its functionality. | 2023-07-07 12:01:27 | 2024-07-08 17:49:16 | 2021-2021 | 6118 | 29581 | % | { "unit": "%", "shortUnit": "%" } |
0 | design | grapher/artificial_intelligence/2023-07-07/semiconductors_cset/semiconductors_cset#design | 1 | [] |
int | [] |
3158d1b5f84bf49037e76906fd4372ef | 0323d52fd5e92608b0e8b76a9ac4f02c |