variables: 737088
Data license: CC-BY
This data as json
id | name | unit | description | createdAt | updatedAt | code | coverage | timespan | datasetId | sourceId | shortUnit | display | columnOrder | originalMetadata | grapherConfigAdmin | shortName | catalogPath | dimensions | schemaVersion | processingLevel | processingLog | titlePublic | titleVariant | attributionShort | attribution | descriptionShort | descriptionFromProducer | descriptionKey | descriptionProcessing | licenses | license | grapherConfigETL | type | sort | dataChecksum | metadataChecksum |
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737088 | Assembly, testing and packaging | % | The completion of the fabrication process yields a finished wafer housing numerous chips in a grid pattern. The subsequent stage is Assembly, which involves testing and packaging. The wafer undergoes division into individual chips or 'dies.' Each chip is mounted on a frame, wired to facilitate connection with external devices, and housed within a protective case. This stage results in the familiar image of a rectangular, dark grey chip with metal pins around the periphery. The chip also undergoes testing to confirm its operational capacity. Historically, Assembly, Test, and Packaging (ATP) was considered a lower value stage. However, with the exponential rise in transistor densities within logic chips, packaging has progressively become a key determinant of chip performance. | 2023-07-07 12:01:27 | 2024-07-08 17:49:16 | 2021-2021 | 6118 | 29581 | % | { "unit": "%", "shortUnit": "%" } |
0 | assembly__testing__and_packaging__atp | grapher/artificial_intelligence/2023-07-07/semiconductors_cset/semiconductors_cset#assembly__testing__and_packaging__atp | 1 | [] |
int | [] |
7ca65a5ea9f158d48885a18083ce88fc | bb36b93d961be705d315ab4198d9066f |