id,name,unit,description,createdAt,updatedAt,code,coverage,timespan,datasetId,sourceId,shortUnit,display,columnOrder,originalMetadata,grapherConfigAdmin,shortName,catalogPath,dimensions,schemaVersion,processingLevel,processingLog,titlePublic,titleVariant,attributionShort,attribution,descriptionShort,descriptionFromProducer,descriptionKey,descriptionProcessing,licenses,license,grapherConfigETL,type,sort,dataChecksum,metadataChecksum
737090,Design,%,"The Design phase encompasses the specification, logic design, physical design, along with validation and verification. The specification outlines the intended operation of the chip within its target system. The logic design phase constructs a schematic model featuring interconnected electrical components. The physical design converts this schematic into a tangible layout of these components and their interconnecting wires. Finally, the design undergoes a validation and verification process to ensure its functionality.",2023-07-07 12:01:27,2024-07-08 17:49:16,,,2021-2021,6118,29581,%,"{""unit"": ""%"", ""shortUnit"": ""%""}",0,,,design,grapher/artificial_intelligence/2023-07-07/semiconductors_cset/semiconductors_cset#design,,1,,,,,,,,,[],,,,,int,[],3158d1b5f84bf49037e76906fd4372ef,0323d52fd5e92608b0e8b76a9ac4f02c
737089,Fabrication,%,"The Fabrication stage morphs these designs into tangible chips. Semiconductor manufacturing plants, known as 'fabs', process the wafers in two primary steps: forming transistors and other electrical devices within silicon wafer layers and creating metallic interconnections among the electrical devices in the insulating layers above the silicon.",2023-07-07 12:01:27,2024-07-08 17:49:16,,,2021-2021,6118,29581,%,"{""unit"": ""%"", ""shortUnit"": ""%""}",0,,,fabrication,grapher/artificial_intelligence/2023-07-07/semiconductors_cset/semiconductors_cset#fabrication,,1,,,,,,,,,[],,,,,int,[],be306bcc260bce71d570f1d7a6ec4227,ad2e51f14bbe1ac2d2ac41f00787962c
737088,"Assembly, testing and packaging",%,"The completion of the fabrication process yields a finished wafer housing numerous chips in a grid pattern. The subsequent stage is Assembly, which involves testing and packaging. The wafer undergoes division into individual chips or 'dies.' Each chip is mounted on a frame, wired to facilitate connection with external devices, and housed within a protective case. This stage results in the familiar image of a rectangular, dark grey chip with metal pins around the periphery. The chip also undergoes testing to confirm its operational capacity.

Historically, Assembly, Test, and Packaging (ATP) was considered a lower value stage. However, with the exponential rise in transistor densities within logic chips, packaging has progressively become a key determinant of chip performance.",2023-07-07 12:01:27,2024-07-08 17:49:16,,,2021-2021,6118,29581,%,"{""unit"": ""%"", ""shortUnit"": ""%""}",0,,,assembly__testing__and_packaging__atp,grapher/artificial_intelligence/2023-07-07/semiconductors_cset/semiconductors_cset#assembly__testing__and_packaging__atp,,1,,,,,,,,,[],,,,,int,[],7ca65a5ea9f158d48885a18083ce88fc,bb36b93d961be705d315ab4198d9066f